Vehicle-onboard driving lane recognizing apparatus

ABSTRACT

A vehicle-onboard driving lane recognizing apparatus of a small scale includes an image pick-up unit ( 1 ) mounted on a motor vehicle for picking up images of scenes making appearance in front of the motor vehicle, an image data selecting unit ( 2 ) for selecting image data only of a predetermined region from the image picked up by the image pick-up unit ( 1 ), an image data storing unit ( 3 ) for storing the image data, and a driving lane recognizing unit ( 4 ) for detecting lane markings ( 21 ) on the road from the image data stored in the image data storing unit ( 3 ) to thereby recognize a driving lane extending along the lane markings ( 21 ). The image data selecting unit ( 2 ), the image data storing unit ( 3 ) and the driving lane recognizing unit ( 4 ) are all implemented in a single chip.

BACKGROUND OF THE INVENTION

This is a divisional of application Ser. No. 10/379,531 filed Mar. 6,2003. The entire disclosures of the prior application, application Ser.No. 10/379,531, is hereby incorporated by reference.

FIELD OF THE INVENTION

The present invention relates to a driving lane recognizing apparatusmounted on a motor vehicle (hereinafter referred to as thevehicle-onboard driving lane recognizing apparatus) for detecting lanemarkings to recognize a driving lane.

DESCRIPTION OF RELATED ART

Heretofore, there have been proposed and developed a great variety ofvehicle-onboard driving lane recognizing apparatuses which are designedfor detecting lane markings or the like existing in front of a runningmotor vehicle to recognize a driving lane therefor.

In general, the conventional vehicle-onboard driving lane recognizingapparatus known heretofore is comprised of a CCD (Charge-Coupled Device)camera serving as an image pick-up means (also known as the imagingmeans) and a recognition processing unit serving as a recognizing means.The CCD camera is installed on, for example, a ceiling portion of themotor vehicle located in the vicinity of a driver seat for picking upimage scenes such as landscapes or the like making appearance in frontof the motor vehicle in the course of running.

In that case, the imaging range of the CCD camera is oriented or setsuch that a road extending for a predetermined distance before the motorvehicle can be covered by the landscape or scene picked up when themotor vehicle is running on the road

On the other hand, the recognition processing unit is comprised of ananalog-to-digital converter (ADC), a pre-processing ASIC (ApplicationSpecified IC), an image memory, a CPU (Central Processing Unit), a ROM(Read-Only memory), a communication IC (Integrated Circuit) and others.

The analog-to-digital converter serves for converting an analog imagesignal outputted from the CCD camera into digital image data. Thepre-processing ASIC executes a predetermined pre-processing on the imagedata outputted from the analog-to-digital converter. As suchpre-processing, there may be mentioned, by way of example, an edgeemphasizing or enhancing filter processing. The image memory is destinedfor storing the image data resulting from the pre-processing.

The CPU executes a processing for the stored image data to recognize thelane markings contained therein.

The RAM serves as a work area for the CPU, while the communication ICserves to transmit to a relevant external system or equipment the datasuch as, for example, the result of recognition of the lane markingstransferred from the CPU. For more particulars, reference may have to bemade to Japanese Patent Application Laid-Open Publication No.213155/1999 (JP-A-11-213155).

In the conventional vehicle-onboard driving lane recognizing apparatusmentioned above, the analog-to-digital converter, the pre-processingASIC, the image memory and the RAM are implemented individually asdiscrete chips, respectively, as a result of which the circuit scale ofthe vehicle-onboard driving lane recognizing apparatus becomes large andinvolves high cost in the implementation thereof giving rise to aproblem.

SUMMARY OF THE INVENTION

In the light of the state of the art described above, it is contemplatedwith the present invention as an object thereof to solve the problemmentioned above by providing an inexpensive vehicle-onboard driving lanerecognizing apparatus of a small circuit scale.

In view of the above and other objects which will become apparent as thedescription proceeds, there is provided according to a general aspect ofthe present invention a vehicle-onboard driving lane recognizingapparatus which includes an image pick-up unit mounted on a motorvehicle running on a road for picking up images of scenes makingappearance in front of the motor vehicle, an image data selecting unitfor selecting image data only of a predetermined region from the imagepicked up by the image pick-up unit, an image data storing unit forstoring the image data, and a driving lane recognizing unit fordetecting lane markings on the road from the image data stored in theimage data storing unit to thereby recognize a driving lane extendingalong the lane markings, wherein at least the image data selecting unit,the image data storing unit and the driving lane recognizing unit areall implemented in a single chip.

By virtue of the arrangement described above, there can be realizedinexpensively the vehicle-onboard driving lane recognizing apparatus ofa small circuit scale while making it unnecessary to install an externalimage data storing unit, to advantageous effect.

The above and other objects, features and attendant advantages of thepresent invention will more easily be understood by reading thefollowing description of the preferred embodiments thereof taken, onlyby way of example, in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

In the course of the description which follows, reference is made to thedrawings, in which:

FIG. 1 is a block diagram showing generally and schematically anarrangement of a vehicle-onboard driving lane recognizing apparatusaccording to a first embodiment of the present invention;

FIG. 2 is a block diagram showing a circuit arrangement of an image dataselecting means according to the first embodiment of the presentinvention;

FIG. 3A is a view illustrating schematically image data selected by theimage data selecting means according to the first embodiment of thepresent invention;

FIG. 3B is a view showing schematically an array of lane markings, asviewed from the top in FIG. 3A;

FIG. 4 is a block diagram showing an arrangement of the vehicle-onboarddriving lane recognizing apparatus according to a second embodiment ofthe present invention;

FIG. 5 is a circuit block diagram showing concretely a circuitconfiguration of an image data transfer rate converting means accordingto the second embodiment of the present invention;

FIG. 6 is a view for graphically illustrating relation between a dotclock signal DCK and a transfer clock signal derived by dividing thefrequency of the dot clock signal by two in the vehicle-onboard drivinglane recognizing apparatus according to the second embodiment of thepresent invention;

FIG. 7 is a block diagram showing an arrangement of the vehicle-onboarddriving lane recognizing apparatus according to a third embodiment ofthe present invention;

FIG. 8 is a block diagram showing an arrangement of an imageinput/output interface of the vehicle-onboard driving lane recognizingapparatus according to the third embodiment of the present invention;

FIG. 9 is a block diagram showing an arrangement of the vehicle-onboarddriving lane recognizing apparatus according to a fourth embodiment ofthe present invention; and

FIG. 10 is a block diagram showing an arrangement of the vehicle-onboarddriving lane recognizing apparatus according to a version of the fourthembodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will be described in detail in conjunction withwhat is presently considered as preferred or typical embodiments thereofby reference to the drawings. In the following description, likereference characters designate like or corresponding parts throughoutthe several views.

Embodiment 1

Now, description will be made of the vehicle-onboard driving lanerecognizing apparatus according to a first embodiment of the presentinvention. FIG. 1 is a block diagram showing an arrangement of thevehicle-onboard driving lane recognizing apparatus according to thefirst embodiment of the invention.

The vehicle-onboard driving lane recognizing apparatus is installed on amotor vehicle running on a road. Referring to FIG. 17 an image pick-upmeans (which may also be referred to as the imaging device or means) 1is designed to pick up images of scenes making appearance in front ofthe motor vehicle, while an image data selecting means 2 is so designedas to select only the image data of specific zones or regions which arerequired for the recognition of a driving lane from those outputted fromthe image pick-up means 1.

An image data storing means 3 is designed to store therein the imagedata selected by the image data selecting means 2. A driving lanerecognizing means 4 is designed to detect lane markings by making use ofthe image data stored in the image data storing means 3 for therebyrecognizing the driving lane extending along the lane markings asdetected.

At this juncture, it should be noted that the image data selecting means2, the image data storing means 3 and the driving lane recognizing means4 are realized en bloc in a single or unitary chip 5 as indicated byenclosing with a single-dotted broken line.

Incidentally, the image pick-up means 1 is shown as being providedexternally of the chip 5. However, it goes without saying that the imagepick-up means 1 may also be implemented on the chip 5 similarly to theother components or means mentioned above, if it is possible,

Next, description will be made in detail of the individual functionalblocks.

At first, the image pick-up means 1 will be elucidated. The imagepick-up means 1 is designed for taking picture or image of scenes makingappearance in front of the motor vehicle in the course of running on aroad. In general, two types of the image pick-up means are well known inthe art. They are a CCD (Charge-Coupled Device) imaging device and aCMOS (Complementary Metal Oxide Semiconductor) imaging device. In thisconjunction, it is presumed that the CMOS imaging device incorporatingtherein an analogue-to-digital converter (ADC) is employed as the imagepick-up means in the vehicle-onboard driving lane recognizing apparatusaccording to the instant embodiment of the invention.

Incidentally, the image pick-up means 1 may be constituted by a CCDserving as the imaging device, a CCD driving IC (Integrated Circuit) andan analogue-to-digital converter (ADC).

Next, description will be directed to the image data selecting means 2.FIG. 2 is a block diagram showing a circuit arrangement of the imagedata selecting means 2 according to the first embodiment of the presentinvention.

Since the circuit arrangement of the image data selecting means 2 isself-explanatory from FIG. 2, description will be directed to operationof the image data selecting means 2. A basic clock signal for drivingthe image pick-up means 1 is inputted to the image pick-up means 1. Whenvarious initial settings for the image pick-up means 1 have beencompleted, a dot clock signal DOCK which changes by one cycle every timethe data of one pixel is outputted from the image data taken by theimage pick-up means 1, while a horizontal synchronizing signal HD and avertical synchronizing signal VD are outputted upon every inputting ofthe basic clock signal.

A horizontal counter 11 designed for counting the number of pixels inthe horizontal direction increments or counts up a count value uponevery inputting of the dot clock signals DCK. The count value of thehorizontal counter 11 is cleared once when the horizontal synchronizingsignal HD is inputted.

The count value outputted from the horizontal counter 11 is compared bya comparator 14 a with a horizontal start address (start address in thehorizontal direction) preset at a horizontal start address hold module12. When the count value becomes greater than the horizontal startaddress, the output of the comparator 14 a changes from a level “L (lowlevel)” to a level “H (high level)”.

Further, the count value outputted from the horizontal counter 11 iscompared by a comparator 14 b with a horizontal end address (end addressin the horizontal direction) placed in a horizontal end address holdmodule 13. So long as the count value remains smaller than thehorizontal end address, the output of the comparator 14 b assumes thelevel “H”, whereas when the count value becomes greater than thehorizontal end address, the output of the comparator 14 b changes to thelevel “L” from “H”.

A logical AND (logical product) circuit 15 a determines a logicalproduct of the outputs of the comparator 14 a and the comparator 14 b.The output signal of the logical AND circuit 15 a serves as the selectsignal in the horizontal direction. Thus, in the horizontal direction,the pixel data located from the horizontal start address to thehorizontal end address are selected from the image data picked up by theimage pick-up means 1.

Similarly, in the vertical direction, a vertical counter 16 designed forcounting the pixel number in the vertical direction increments the countvalue thereof in response to inputting of the horizontal synchronizingsignal HD. The count value of the vertical counter 16 is once clearedwhen the vertical synchronizing signal VD is inputted.

The count value outputted from the vertical counter 16 is compared by acomparator 14 c with a vertical start address (start address in thevertical direction) preset at a vertical start address hold module 17.When the count value becomes greater than the vertical start address,the output of the comparator 14 c changes from a level “L” to a level“H” to be outputted.

Further, the count value outputted from the vertical counter 16 iscompared by a comparator 14 d with a vertical end address (end addressin the vertical direction) placed in a vertical end address hold module18. So long as the count value remains smaller than the vertical endaddress, the output of the comparator 14 d assumes the level “H”,whereas when the count value becomes greater than the vertical endaddress, the output of the comparator 14 d changes to the level “L” from“H”.

A logical AND circuit 1 Sb determines a logical product of the outputsof the comparator 14 c and the comparator 14 d. The output signal of thelogical AND circuit 15 b serves as the select signal in the verticaldirection. In other words, in the vertical direction, the pixel datalocated from the vertical start address to the vertical end address areselected from the image data picked up by the image pick-up means 1.

Finally, the output of the logical AND circuit 15 a representing theselect signal in the horizontal direction and the output of the logicalAND circuit 15 b representing the select signal in the verticaldirection are logically ANDed by a logical AND circuit 15 c, whereby theimage data select signal for one rectangular select range is generated.

By making use of the generated select signal, the image data is selectedto be subsequently stored in the image data storing means 3 of thesucceeding stage.

Incidentally, the image data selecting means shown in FIG. 2 is soarranged as to select one rectangular region or zone. In thisconjunction, it is to be added that in the case where a plurality ofregions or zones are to be selected, a corresponding number of the imagedata selecting means each of the structure similar to that shown in FIG.2 may be provided.

Further, although it has been described that the image data selectingmeans shown in FIG. 2 is realized by employing hardware such as thecounters, comparators, etc., it goes without saying that the image dataselecting means may be implemented by a microcomputer which is comprisedof a CPU (Control Processing Unit), a RAM (Random Access Memory) and atimer at the least. In that case, the image selection may be realized bymaking use of the output signal waveform of the timer incorporated inthe microcomputer.

In this conjunction, it should further be added that the image dataselecting means 2, the image data storing means 3, and the driving lanerecognizing means 4 may be realized by a microcomputer, as will bedescribed hereinafter. In that case, it is preferred to realize theimage selection by making use of the output signal of the timer, becausethen the circuit scale can be made small with the cost being reduced.

Besides, by selecting the image by means of software incorporated In themicrocomputer, it is possible to change dynamically the select range ofthe image data in dependence on the recognized state of the drivinglane.

Additionally, the whole image may be selected by designating the startaddress and the end address in both the horizontal and verticaldirections, as the case may be.

Next, referring to FIGS. 3A and 38, description will be made as to whatsort of the image data is selected by the image data selecting means 2for the recognition of the driving lane. FIGS. 3A and 3B are views forillustrating the image data selected in the vehicle-onboard driving lanerecognizing apparatus according to the first embodiment of the presentinvention.

According to a method adopted generally for recognizing the drivinglane, search zones are set for detecting lane markings 21 painted on aroad. In FIG. 3A, a plurality of search regions or zones 22 a to 22 fset for the recognition of the driving lane are exemplarily illustrated.

In this conjunction, it is noted that although a single search region orzone is defined by a rectangular region of (M×N) pixels with M pixels inthe horizontal direction and N pixels in the vertical direction, where Mand N represent given natural number, respectively, the search zone maybe derived as a search line with the pixel number N in the verticaldirection being one.

As shown in FIG. 3A, the search regions or zones are disposed on theroad image lying beneath the horizon, starting from the top of the roadimage.

FIG. 3B is a top plan view of the image shown in FIG. 3A. As shown inFIG. 3B, it is preferred to dispose the search regions or zonesorthogonally relative to the running or traveling direction of the motorvehicle substantially with equidistance among the search zones in thetraveling direction for the reason described later on. As the searchzones or regions for detecting the lane markings, there can be conceivedother varieties. However, description thereof is omitted.

The image data of the individual search zones or regions selected by theimage data selecting means 2 are stored in the image data storing means3.

The driving lane recognizing means 4 detects the lane markings byprocessing the image data stored in the image data storing means 3 tothereby recognize a driving lane extending along the lane markings.

Next, description will be directed to the recognition of the drivinglane as carried out by the driving lane recognizing means 4. Asdescribed previously, the position at which the lane marking exists inthe selected search zone or region is detected. As the lane markingdetecting method, there may be mentioned a conventional filterprocessings such as template matching or the like.

For effectuating the template matching, a template which exhibits aluminance distribution similar to that of the object to be detected isprepared, and the one exhibiting the highest correlation with thetemplate is selected as the object concerned.

By way of example, presuming that the search zone shown in FIG. 3A arein the form of a search line, pulses of the luminance signal indicatethe positions of the lane markings exhibiting high luminance. Further,by preparing a one-dimensional template for the lane marking andshifting the template bit by bit, for example, from the left, differencebetween the luminance signals is determined to thereby detect thelocation where the difference is greatest. Thus, it is decided that thelocation mentioned above exhibits the highest correlation with thetemplate. In other words, it can be determined that the locationmentioned above indicates the position of the lane marking.

On the basis of the positions of the lane markings detected in theindividual search zones, respectively, the parameter representing thedriving lane (road geometry) which can be represented by a polynomial orthe like can be identified to be the result of recognition of thedriving lane.

As described previously, by selectively setting the individual searchzones such that they are disposed substantially with equidistance in thetraveling direction, as viewed from the top, the detected positions ofthe lane markings will also lie with equidistance therealong. Thus, theparameter of the driving lane expressed by the polynomial or the likecan be identified without any difficulty.

Next, description will be made of the single-dotted line block 5 shownin FIG. 1. The block 5 incorporating the image data selecting means 2,the image data storing means 3 and the driving lane recognizing means 4,as shown in FIG. 1, is realized as a single chip. In this conjunction,it is to be noted that the term “chip” used herein is used to meanprimarily the chip dedicated to the image processing, i.e., imageprocessing dedicated chip. It should however be understood that suchchip can be realized by a microcomputer incorporating therein as theindispensable components a CPU, a RAM and a timer at the least.Accordingly, the term “chip” used herein is to be interpreted such thatthe microcomputer chip is covered as well.

In recent years, the capacity of the RAM incorporated integrally in themicrocomputer tends to increase. However, the microcomputerincorporating the RAM of a large capacity capable of storing all theimage data of, for example, 640×480 pixels, which is termed generallyVGA (video graphics array) according to the video standards for PC,while allowing the program to run, is extremely expensive.

Such being the circumstances, according to the teachings of the presentinvention incarnated in the instant embodiment thereof, it is taughtthat the image data selecting means 2, the image data storing means 3and the driving lane recognizing means 4 at the least are realized inone and the same chip, wherein only the image data of the specificregion required for the recognition of the driving lane is selected bythe image data selecting means 2 to be subsequently transferred to theimage data storing means 3 (i.e., the so-called built-in RAM). By virtueof this arrangement, the built-in RAM can be of a small capacity andthus the chip can be realized significantly at very low cost. In otherwords, according to the teaching of the present invention incarnated inthe instant embodiment, the vehicle-onboard driving lane recognizingapparatus of small circuit scale and low cost can be realizedadvantageously for practical applications.

At this juncture, it should also be added that so far as all the imagedata required for the recognition of the driving lane can be stored inthe built-in RAM, there arises no necessity of providing an extraneousRAM externally of the chip to another advantage.

Furthermore, in the conventional vehicle-onboard image processingsystem, the image data is not intactly stored but a primitive processingcalled a so-called pre-processing such as typified by a simple filteringprocessing of the image data is performed by employing a dedicated ICsuch as an ASIC (application-specific integrated circuit) or the like.By contrast, in the case of the vehicle-onboard driving lane recognizingapparatus according to the instant embodiment of the invention, all theimage data1 are saved in the RAM incorporated in the chip 5 or themicrocomputer chip. Accordingly, the pre-processing mentioned above canwholly be carried out softwarewise by taking advantage of high-seedaccess capability.

As is obvious from the above, extraneous external RAM and the dedicatedIC such as application-specific integrated circuit can be spared,whereby the size or scale as well as the cost of the apparatus canremarkably be reduced.

Embodiment 2

In the vehicle-onboard driving lane recognizing apparatus according tothe first embodiment of the present invention described above, noconsideration has been paid to the transfer rate of the image data.According to the teaching of the invention incarnated in a secondembodiment, there is adopted an arrangement for converting the transferrate of the data derived from the output of the image pick-up means 1.

FIG. 4 is a block diagram showing an arrangement or structure of thevehicle-onboard driving lane recognizing apparatus according to thesecond embodiment of the present invention. Incidentally, componentssame as or equivalent to those described hereinbefore by reference toFIG. 1 are denoted by like reference numerals and repeated descriptionin detail thereof will be omitted.

Referring to FIG. 4, the vehicle-onboard driving lane recognizingapparatus according to the instant embodiment of the invention isprovided with a pixel data transfer rate converting means 31 forconverting the transfer rate of the pixel data of the image picked up bythe image pick-up means 1.

At this juncture, it should be mentioned that the single-dotted brokenline block 5 may be implemented as a single chip. In that case, only theimage pick-up means 1 is provided externally of the chip 5. It goeshowever without saying that in case the image pick-up means 1 can beincorporated in the chip 5, it may be built in the chip similarly to theother means or components. Furthermore, although the block 5 may beconstituted by a dedicated IC for the image processing, it is presumedthat in the vehicle-onboard driving lane recognizing apparatus accordingto the instant embodiment of the invention, the block 5 is constitutedby a microcomputer which includes as the indispensable components a CPU,a RAM and a timer at the least.

Description will now be directed to the operation of the pixel datatransfer rate converting means 31. In the case where the output rate ofthe pixel data is lower than the transfer rate inherent to themicrocomputer, it is possible to input the image data delivered from theimage pick-up means intactly to the RAM incorporated in themicrocomputer. On the other hand, when the output rate of the pixel datais higher than the transfer rate inherent to the microcomputer, theimage data can be fetched by the microcomputer by lowering the transferrate of the pixel data by adopting the arrangement shown in FIG. 5, aswill be described below.

More specifically, by making use of a dot clock signal which changes byone cycle every time the pixel data of one pixel (picture element) isoutputted from the image pick-up means, the pixel data can betransferred to the built-in RAM of the microcomputer at the transferrate corresponding to 1/M of the output rate of one pixel data, where Mrepresents a given natural number.

FIG. 5 is a circuit block diagram showing concretely a circuitconfiguration of the pixel data transfer rate converting means 31.Referring to FIG. 5, operation of the pixel data transfer rateconverting means 31 will be described below on the presumption that M isequal to “2”.

The pixel data outputted sequentially from the image pick-up means 1 aresupplied to input ports D[7..0] of D-flip-flops (DFFs) 36 and 37 to bestored in the D-flip-flops 36 and 37 under the timing of the dot clocksignal DCK which changes by one cycle every time one pixel of the pixeldata is outputted.

In this conjunction, it is to be noted that the pixel data outputtedfrom the output port Q[7..0] of the D-flip-flop 37 temporally proceedsby one pixel relative to the pixel data outputted from the output portQ[7..0] of the D-flip-flop 36.

On the other hand, the frequency of the dot clock signal DCK is loweredto a half by means of a frequency by-two-division circuit which may berealized by a T-flip-flop (TFF) 38. Relation between the original dotclock signal DCK and the transfer clock whose frequency is equal to aquotient resulting from division of the dot clock OCK by two is such asillustrated in FIG. 6.

When pixel data of two pixels have been inputted with two dot clocksDCK, the pixel data of two pixels are transferred to the microcomputer.

In this manner, two pixel data each of 8 bits which temporally continueto each other are made available from the outputs of the D-flip-flops 36and 37 to be transferred to the built-in RAM of the microcomputer fromthe 16-bit transfer port under the timing of the transfer clock signal.

As is apparent from the foregoing, with the circuit arrangementdescribed above, it is possible to fetch the image data on a real-timebasis even when the transfer rate at which the pixel data is transferredto the built-in RAM of the microcomputer is lower than the output rateof the pixel data outputted from the image pick-up means 1 by latching apredetermined number of pixel data and by transferring en bloc the pixeldata when the predetermined number of the pixel data have been latched.

In this manner, by realizing the pixel data transfer rate convertingmeans 31 for converting the transfer rate of the image data with asimplified structure, the select range of the microcomputer can bebroadened, which in turn means that the microcomputer of low cost andlow transfer rate can be employed while mitigating limitation imposed onthe built-in RAM capacity of the microcomputer similarly to the case ofthe first embodiment of the invention, whereby the total cost demandedfor the vehicle-onboard driving lane recognizing apparatus can bereduced.

Embodiment 3

In the case of the vehicle-onboard driving lane recognizing apparatusfirst and second embodiments of the present invention, the image dataoutputted from the image pick-up means 1 are fetched for use. Accordingto the teaching of the present invention incarnated in a thirdembodiment thereof, image data available from an external system orequipment can also be made use of.

FIG. 7 is a block diagram showing an arrangement or structure of thevehicle-onboard driving lane recognizing apparatus according to thethird embodiment of the present invention. Incidentally, in FIG. 7,components same as or equivalent to those described hereinbefore byreference to FIGS. 1 and 4 are denoted by like reference numerals andrepeated description in detail thereof will be omitted.

Referring to FIG. 7, in the vehicle-onboard driving lane recognizingapparatus according to the instant embodiment of the invention, all theimage data derived from the output of the image pick-up means 1 are alsooutputted to an external system or equipment. The vehicle-onboarddriving lane recognizing apparatus now under consideration is providedwith an image input/output interface 41 which is so designed as totransfer the image data inputted from the external system or equipmentto the image data storing means 3 by way of the image data selectingmeans 2 in place of the image data outputted from the image pick-upmeans 1, when the image data is supplied from the external system orequipment.

FIG. 8 is a block diagram showing an arrangement or structure of theimage input/output interface 41 of the vehicle-onboard driving lanerecognizing apparatus according to the third embodiment of the presentinvention. Incidentally, components same as or equivalent to thosedescribed hereinbefore by reference to FIGS. 1, 4 and 7 are denoted bylike reference numerals and repeated description in detail thereof willbe omitted.

At this juncture, it should also be mentioned that the single-dottedbroken line block 5 may be implemented as in the form of a single chip.In that case, only the image pick-up means 1 is provided externally ofthe chip 5. It goes however without saying that in case the imagepick-up means 1 can be incorporated in the chip 5, it may be built inthe chip similarly to the other means or constituents.

Now referring to FIG. 8, an external image input decision module 46 isdesigned to make decision as to whether or not the image data isinputted from the external system and output a decision signal EXTIN oflevel “H” when it is determined that the image data is inputtedexternally. On the other hand, when it is determined that no externalimage data input exists, the external image input decision module 46outputs the decision signal EXTIN of level “L”.

The decision signal EXTIN is used as a gate signal for three-statebuffers 47 a and 47 b, respectively. Unless the image data is inputtedfrom the external system, the image data derived from the output of theimage pick-up means 1 is delivered intactly from the output of thethree-state buffer 47 a since the decision signal EXTIN is of “L” level,while the output of the three-state buffer 47 b exhibits a highimpedance.

Consequently, in the above-mentioned case, the image data outputted fromthe image pick-up means 1 are transferred to the image data storingmeans 3 by way of the image data selecting means 2 and at the same timethe image data outputted from the image pick-up means 1 are supplied tothe external system through image output line.

On the other hand, in the case where the image data are inputted fromthe external system, the decision signal EXTIN will then assume thelevel “H”. In that case, the output of the three-state buffer 47 aexhibits high impedance, whereby the externally inputted image datadelivered from the output of the three-state buffer 47 b are transferredto the image data storing means 3 via the image data selecting means 2.Further, the externally inputted image data is supplied to the externalsystem through the image output line as well.

By virtue of the arrangement of the vehicle-onboard driving lanerecognizing apparatus described above, even through only the image dataof a given limited region or zone can be stored internally of theapparatus, the whole image can also be observed or confirmed because allthe image data are outputted externally.

Furthermore, in the case where the image data is available from theexternal system or equipment, the image data can be transferred to theimage data storing means 3 incorporated in the apparatus. Then, theimage data taken upon running or driving test or for the other purposemay be inputted from a relevant external system or equipment to therebylogically examine the driving lane recognition processing on a desk,

At this juncture, it should be mentioned that substantially only thethree-state buffers 47 a and 47 b are additionally incorporated in theapparatus for realizing the function described above. In other words,the functions for checking or observing the whole image as well as forthe logical examination on the desk can be added without increasingappreciably the control signal of the whole apparatus.

Embodiment 4

In the description of the first to third embodiments of the invention,no consideration has been paid to the basic clock signal supply. Thevehicle-onboard driving lane recognizing apparatus according to a fourthembodiment of the present invention is so arranged that the individualmeans thereof are driven on the basis of a basic clock signal suppliedfrom a single oscillator.

Referring to FIG. 9, the vehicle-onboard driving lane recognizingapparatus is provided with an oscillator 51 for supplying the basicclock signal to the image pick-up means 1 and the block 5, wherein theimage pick-up means 1 is comprised of an image-pickup device 1 a and adedicated driving signal generating means 1 b which is dedicated fordriving the image-pickup device 1 a.

In operation, the basic clock signal supplied to the image pick-up means1 from the oscillator 51 is inputted to the dedicated driving signalgenerating means 1 b incorporated in the image pick-up means 1.

The dedicated driving signal generating means 1 b is designed togenerate various driving signals such as the horizontal synchronizingsignal HD and the vertical synchronizing signal VD for driving theimage-pickup device 1 a and others.

The generated driving signals are inputted to the image-pickup device 1a for driving the same. The image-pickup device 1 a outputs the imagedata which are then stored In the image data storing means 3 by way ofthe image data selecting means 2.

The driving lane recognizing means 4 executes the processing forrecognizing the driving lane by making use of the image data stored inthe image data storing means 3. Parenthetically, operation of thedriving lane recognizing means 4 is similar to that describedhereinbefore in conjunction with the preceding embodiments of theinvention. Accordingly, repeated description will be unnecessary.

At this juncture, it is to be noted that the basic clock signal fordriving the image pick-up means 1 is in common to the clock for drivingthe image data selecting means 2, the image data storing means 3 and thedriving lane recognizing means 4.

In the case of the conventional vehicle-onboard driving lane recognizingapparatus, the basic clock signal for driving the image pick-up means 1is prepared separately from the clock signal for driving the other unitsthan the image pick-up means 1 in view of the video signal standards. Bycontrast, in the vehicle-onboard driving lane recognizing apparatusaccording to the instant embodiment of the invention, the basic clocksignal is commonly used for driving not only the image pick-up means 1and the other portions (e.g. block 5). In other words, employment of thesingle oscillator is sufficient. Owing to this feature, the timingcircuit design can be simplified and facilitated.

Further, for driving the image pick-up means 1 together with the otherunits with the common basic clock signal, such arrangement as shown inFIG. 10 can also be adopted.

FIG. 10 is a block diagram showing an arrangement or structure of thevehicle-onboard driving lane recognizing apparatus according to thefourth embodiment of the present invention. Incidentally, in FIG. 10,components same as or equivalent to those described hereinbefore byreference to FIGS. 1, 4, 7 and 9 are denoted by like reference numeralsand repeated description in detail thereof will be omitted.

In the vehicle-onboard driving lane recognizing apparatus shown in FIG.10, the block 5 is realized as a microcomputer which includes a CPU, aRAM and a timer at the least as the indispensable components. Thismicrocomputer operates under the timing of the basic clock signalsupplied from the oscillator 51.

In the vehicle-onboard driving lane recognizing apparatus shown in FIG.9, the driving signal for driving the image-pickup device 1 a isgenerated by the dedicated driving signal generating means 1 b. On theother hand, in the case of the vehicle-onboard driving lane recognizingapparatus shown in FIG. 10, the driving signal mentioned above isgenerated by the timer incorporated in the microcomputer. Accordingly,the dedicated driving signal generating means 1 b which is required fordriving the image-pickup device 1 a in the vehicle-onboard driving lanerecognizing apparatus shown in FIG. 9 can be spared in thevehicle-onboard driving lane recognizing apparatus shown in FIG. 10.Thus, the vehicle-onboard driving lane recognizing apparatus shown inFIG. 10 can be realized on a much smaller scale basis when compared withthat shown in FIG. 9.

As can be understood from the above, by driving the image pick-up means1 and the other components with a common clock signal, it is sufficientto employ only one oscillator 51, which means that the vehicle-onboarddriving lane recognizing apparatus can be manufactured at low cost.Besides, because the components or means incorporated in thevehicle-onboard driving lane recognizing apparatus are driven by thecommon clock signal, the arrangement for timing properly the operationof these means can easily be designed and implemented.

Further, by generating the driving signal for driving the image-pickupdevice 1 a by means of the built-in timer 52 incorporated in themicrocomputer as in the case of the vehicle-onboard driving lanerecognizing apparatus shown in FIG. 10, the circuit scale can further bereduced.

It should however be mentioned that although the image pick-up means 1and the other components or means are operated under the timing of theone and the same clock signal in the vehicle-onboard driving lanerecognizing apparatus according to the instant embodiment of theinvention, such arrangement may of course be adopted that the basicclock signal for driving the image pick-up means 1 is N times as high asthe clock signal for operating the other means or components oralternatively the frequency of the basic clock signal for driving theimage pick-up means 1 may be 1/N of that of the clock signal for drivingthe other means or components, where N represents a given naturalnumber.

The block 5 indicated as enclosed by the single-dotted broken line maybe realized in one chip. In that case, only the image pick-up means 1 isprovided externally of the single-dotted line block 5. It should howeverbe appreciated that the image pick-up means 1 may be incorporated in thechip 5 together with the other means or components if it is possible.

In general, the exposure control based on the luminance information ofthe whole image will incur essentially no problem. However, in the caseof the vehicle-onboard image processing apparatus, it is preferred toprevent the luminance information of the unnecessary image region frombeing reflected in the exposure control. In other words, the exposurecontrol should ideally be performed by making use of the luminanceinformation of a concerned or relevant portion of the image. In thatcase, a luminance measuring timing signal is required for measuringluminance of the concerned portion of the image in synchronism with theoperation timing of the image pick-up means 1. In this conjunction, itshould be noted that because the same basic clock signal is employedcommonly for all the components of the vehicle-onboard driving lanerecognizing apparatus realized in the arrangement shown in FIG. 10, theluminance measuring timing signal can equally be derived from the outputof the timer incorporated in the microcomputer.

Many modifications and variations of the present invention are possiblein the light of the above techniques. It is therefore to be understoodthat within the scope of the appended claims, the invention may bepracticed otherwise than as specifically described.

1. A vehicle-onboard driving lane recognizing apparatus, comprising:image pick-up means mounted on a motor vehicle running on a road forpicking up images of scenes making appearance in front of said motorvehicle to thereby output picked-up images in the form of pixel data;image data transfer rate converting means for converting transfer rateof said pixel data for transferring said pixel data at a convertedtransfer rate; image data selecting means for selecting the image dataof a predetermined region from image data constituted by a set of saidpixel data outputted from said pixel data transfer rate convertingmeans; image data storing means for storing the image data selected bysaid image data selecting means; and driving lane recognizing means fordetecting lane markings on said road from the image data stored in saidimage data storing means to thereby recognize a driving lane extendingalong said lane markings, =p1 wherein representing the number of saidpixel data by M while representing the number of bits of said pixel databy N (where M and N are given natural numbers, respectively), said pixeldata transfer rate converting means is so arranged as to transform Mpixel data each of N bits into a single (M×N)-bit data for therebytransferring said (M×N)-bit data to said image data selecting means enbloc through a single transfer at a time point when M pixel data each ofN bits have been held.
 2. A vehicle-onboard driving lane recognizingapparatus according to claim 1, said image data selecting means saidimage data storing means and said driving lane recognizing means beingrealized by a microcomputer which incorporates therein software forselecting the image data of said predetermined region and a timer,wherein said image data selecting means is so designed as to select theimage data in dependence on high level and low level of an output signalof said timer while changing dynamically selection-subjected objectscontained in said image data.
 3. A vehicle-onboard driving lanerecognizing apparatus according to claim 1, further comprising: anoscillator designed to output a basic clock signal for controlling saidimage data selecting means, said image data storing means and saiddriving lane recognizing means, wherein a control signal for controllingsaid image pick-up means is generated on the basis of said basic clocksignal.
 4. A vehicle-onboard driving lane recognizing apparatusaccording to claim 1, said image data selecting means, said image datastoring means and said driving lane recognizing means being realized bya microcomputer which incorporates therein a timer, wherein an outputsignal of said timer is made use of as a control signal for controllingsaid image pick-up means.
 5. A vehicle-onboard driving lane recognizingapparatus according to claim 1, wherein said image data selecting meansis so arranged as to select a plurality of predetermined regions on aroad which corresponds to an image located beneath the horizon from animage picked up by said image pick-up means, said plurality ofpredetermined regions extending orthogonally to a traveling direction ofsaid motor vehicle substantially with equidistance among saidpredetermined regions as viewed in the traveling direction of said motorvehicle.